The present invention relates, in general, to logic circuits and, more particularly, to a relatively high speed output drive circuit compatible with Emitter-Coupled Logic (ECL) to Transistor-Transistor Logic (TTL) translator circuits for boosting the output high voltage (V.sub.OH) to nearly the positive supply rail.
ECL-to-TTL translator logic circuits are well known in the art. For example, U.S. Pat. No. 4,939,393 describes a single power supply PECL to TTL translator circuit of the type to which the present invention is related. The '393 translator circuit uses a NPN bipolar output drive transistor for speed to minimize the propagation time delay of the circuit as the output transitions from a low output voltage to a high output voltage. Thus, as the NPN transistor is rendered conductive it sources current to the output of the circuit for driving the output positive.
Although the above described prior art circuit works quite well with positive power supply voltages equal to or greater than five volts, a problem is encountered as the power supply voltage is reduced, for example, to a magnitude of three (3) volts, which is required in some logic circuits of the type described above. At best, prior art circuits using a NPN bipolar output transistor can pull V.sub.OH to within only a base-emitter voltage, V.sub.BE, of the positive power supply voltage. If, for example, the power supply voltage is 3.0 volts and V.sub.BE is typically 0.9 volts, V.sub.OH can only be pulled up to approximately 2.1 volts. This condition will not meet the Joint Electron Device Engineering Council (JEDEC) specification of V.sub.OH being equal to or greater than 2.4 volts with VEE=0 VDC and V.sub.CC.gtoreq.3.0 VDC.
Hence, a need exists for a high speed ECL to TTL translator circuit in which the output drive circuitry is capable of meeting the JEDEC TTL V.sub.OH specification of .gtoreq.2.4V with V.sub.CC.gtoreq. 3.0V and VEE+0V.